[PATCH 1/3] Support for PCI Express reset type

Linas Vepstas linasvepstas at gmail.com
Sun Aug 2 08:40:27 EST 2009

Hi Andi,

2009/7/31 Andi Kleen <andi at firstfloor.org>:
> Mike Mason <mmlnx at us.ibm.com> writes:
>> These patches supersede the previously submitted patch that
>> implemented a fundamental reset bit field.
>> Please review and let me know of any concerns.
> Any plans to implement that for x86 too? Right now it seems to be a PPC
> specific hack.

I've found the PCIE chipsepc somewhat daunting, but was under the
impression that much if not most of what was needed was specified

See, for example:

which states:
|||   The PCI Express Advanced Error Reporting Driver Guide HOWTO
|||                T. Long Nguyen  <tom.l.nguyen at intel.com>
|||                Yanmin Zhang    <yanmin.zhang at intel.com>
|||                                07/29/2006
||| The PCI Express AER driver provides the infrastructure to support PCI
||| Express Advanced Error Reporting capability. The PCI Express AER
||| driver provides three basic functions:
||| -       Gathers the comprehensive error information if errors occurred.
||| -       Reports error to the users.
||| -       Performs error recovery actions.

I presume the last bullet point  means that the AER code works and
actually does more or less the same thing as the PPC EEH code,
but in a more architecture-independent way, as it only assumes
that PCI AER is there (and is correctly implemented in the CPI chipset)
The AER code uses the same core infrastructure as the EEH code,
at the time, I did exchange emails w/ the above authors discussing
this stuff.

As to whether the x86 server vendors are actually selling something
with AER in it, and whether any of them are actually testing this stuff
is unclear.

FWIW IBM has pretty much no incentive to lobby other server vendors
to get on the ball ...as this is viewed as one of those things that lets
IBM charge premium prices for PPC hardware.


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