Question about DBCR0 initialization for 440
John.Linn at xilinx.com
Sat Apr 18 06:30:45 EST 2009
> -----Original Message-----
> From: Grant Likely [mailto:grant.likely at secretlab.ca]
> Sent: Friday, April 17, 2009 1:10 PM
> To: Benjamin Herrenschmidt
> Cc: Hollis Blanchard; linuxppc-dev at ozlabs.org; John Linn;
> Tirumala Reddy Marri
> Subject: Re: Question about DBCR0 initialization for 440
> On Fri, Apr 17, 2009 at 1:04 PM, Benjamin Herrenschmidt
> <benh at kernel.crashing.org> wrote:
> > On Fri, 2009-04-17 at 13:07 -0500, Hollis Blanchard wrote:
> >> On Friday 17 April 2009 12:22:37 Josh Boyer wrote:
> >> > On Fri, Apr 17, 2009 at 11:46 AM, John Linn
> <John.Linn at xilinx.com> wrote:
> >> > > Josh, any thoughts on putting this into head_44x.S?
> >> >
> >> > The code in the fsl file looks like the right solution.
I do have an
> >> > odd question though, in that it's hard for the
> >> > kernel to really know if something like a BDI is
> running. Namely,
> >> > that config option doesn't cover RiscWatch in an obvious manner.
> >> Yeah, setting DBCR0 would interfere with all JTAG probes.
> The ifdef meands you
> >> can't support both a JTAG debugger and hardware
> breakpoints in the same
> >> binary? Now that's an annoying restriction.
> > Might be worth checking if external debug is enabled, and
> override it
> > only if it's not.
> ppc440x5_um.pdf says that both can be enabled.
The code that I started the thread with, from the fsl file, has conditional for the BDI around it.
We think that we still need that conditional as the code is not Oring in the enable such that it would
disable external debug mode for the BDI. But we need it this way for our Xilinx pod.
* The Abatron BDI JTAG debugger does not tolerate others
* mucking with the debug registers.
lis r2,DBCR0_IDM at h
/* clear any residual debug events */
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
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