demuxing irqs

[Roland Dreier]

 > The muxed interrupts are inside a SOC CPU.  For example eight GPIOs
 > can each individually be enabled to trigger hardware interrupt 7. When
 > I get hw interrupt 7 i want to demux it into 8 virtual interrupts.
 > There are eight bit registers for individually acking, enabling, etc
 > each of the eight multiplexed interrupts. With eight virutal
 > interrupts each user can register a different handler and isn't aware
 > the muxing is going on.

I see... well, assuming all the issues around handling multiple
simultaneous (or overlapping) interrupts are OK, you could look at how
arch/powerpc/sysdev/uic.c handles the cascaded interrupt controllers for
4xx SoCs.  The idea of that code is that you get an interrupt, and look
look at interrupt cause register 0, and see interrupt X, and to handle
interrupt X you read interrupt cause register 1 to see which the real
interrupt is.  And you might see interrupt Y, which means to go onto
interrupt cause register 2.

 - R.