[PATCH] powerpc: add support for PAGE_SIZEs greater than 4KB for

[prodyut hazarika]

>
> I think you missed first '-' on the first line.
>
I was not too careful :-)


>> I think these 44x specific defines should go to asm/mmu-44x.h since I
>>
>
> Agreed.
>
It would be great to have user-friendly names.
Also moving to the mmu-4xx specific header files hides the changes to 4xx files.


>> For 256KB page size, I cannot understand why PTE_SHIFT is 11. Since
>> each PTE entry is 8 byte, PTE_SHIFT should have been 15. But then
>> there would be no bits in the Effective address for the 1st level
>> PGDIR offset. On what basis PTE_SHIFT of 11 is chosen? This overflow
>> problem happens only for 256KB page size.
>>
>
> I think Yuri has commented on this already.
>
Thanks.

In file arch/powerpc/mm/pgtable_32.c, we have:

#ifdef CONFIG_PTE_64BIT
/* 44x uses an 8kB pgdir because it has 8-byte Linux PTEs. */
#define PGDIR_ORDER     1
#else
#define PGDIR_ORDER     0
#endif
pgd_t *pgd_alloc(struct mm_struct *mm)
{
        pgd_t *ret;

        ret = (pgd_t *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, PGDIR_ORDER);
        return ret;
}

Thus, we allocate 2 pages for 44x processors for PGD. This is needed
only for 4K page.
We are anyway not using the whole 64K or 256K page for the PGD. So
there is no point to waste an additional 64K or 256KB page

Change this to:
#ifdef CONFIG_PTE_64BIT
#if (PAGE_SHIFT == 12)
/* 44x uses an 8kB pgdir because it has 8-byte Linux PTEs. */
#define PGDIR_ORDER     1
#else
#define PGDIR_ORDER     0
#endif
#else
#define PGDIR_ORDER     0
#endif