Extended Addressing Mode

[Matt Sealey]

Kumar Gala wrote:
> 
> On Oct 22, 2008, at 9:22 AM, Matt Sealey wrote:
> 
>> ~~
>> The CCSR window always takes precedence over all local access windows. 
>> However, the CCSR window must not overlap an LAW that maps to the DDR 
>> controller. Otherwise, undefined behavior occurs.
>> ~~
>>
>> So, it's not really possible to map 4GB of RAM in the lower 32-bit 
>> area, without interacting badly with the CCSR. This means you're 
>> forced to select a 2GB LAW for DDR, then leave 2GB free, then map the 
>> rest above.. using more than 2Gb therefore absolutely requires 
>> non-contiguous memory..?
> 
> As I said, its all about your physical DDR layout.  If you have two DDR 
> dimms each 2Gb you can do:
> 
> 0..2G  - DDR DIMM A
> 2G..4G - IO
> 4G..6G - DDR DIMM B

I assume on the HPCN "DDR DIMM A" would be one or both of one 
set of DDR slots, and DDR DIMM B would be one or both o the 
other set (since there are 4 slots, two for each controller)?

Or are we talking about actual, physical DIMMs?

If we're talking about controllers, could you not do;

0..2GB DDR Controller 1 (partial)
2G..4GB IO
4GB..NGB DDR Controller 1 (the rest)
NGB-64GB DDR Controller 2 (or whatever)

Or do LAWs not cooperate when for the same target? I would 
assume if you set up the CSn_BNDS registers right you could 
get a real fine grained mapping of DDR controller to memory 
space in combination with the LAWs? It would then be actually 
possible (however disgusting this config would be) to have a 
2GB DIMM, 1GB DIMM on the first controller with two LAWs, and 
the appropriate chip selects, then 1GB IO space, then up to 
32GB (since 16GB DIMMs are about as high as it goes for DDR2) 
memory space mapped after that, with a single LAW?

Or more comfortably, pair up 2x 2GB DIMMs and simply ignore 
the last 1GB, and pair up 2x 16GB DIMMs?

-- 
Matt Sealey <matt at genesi-usa.com>
Genesi, Manager, Developer Relations