[PATCH] powerpc: GE Fanuc's FPGA based PIC controller on the SBC610
Martyn Welch
martyn.welch at gefanuc.com
Wed Oct 1 17:56:30 EST 2008
On Tue, 30 Sep 2008 12:08:47 -0500
Scott Wood <scottwood at freescale.com> wrote:
> On Tue, Sep 30, 2008 at 03:29:42PM +0100, Martyn Welch wrote:
> > + gef_pic: pic at 4,4000 {
> > + #interrupt-cells = <2>;
>
> What is the second interrupt cell for, given that all interrupts are
> level-triggered and you don't implement .set_type?
>
An error I guess. Queue v3 ;-)
Thanks,
Martyn
> -Scott
--
Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748
GE Fanuc Intelligent Platforms Ltd, |Registered in England and Wales
Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square,
Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 729849476
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