AMCC PPC460EX Canyonlands does not see PCIe end point with only non-prefetchable memory (both 2.6.27.7 and -next)

[Leon Woestenberg]

Hello,

AMCC PPC460EX Canyonlands development board with PCI Express x1 card
in PCIe x4 slot labeled 'PCIE-1'. The PCI Express card has a
soft-programmable PCIe end point.

Problem: The end point with only non-prefetchable BAR does not appear
behind the PPC SoC internal bridge. It does show up on two other
setups: MPC8315E-RDB PPC as well as a PC x86.
It has BARs 0-5 each as a 32-bit non-prefetchable memory region. This
is the kernel boot:

pci 0001:80:00.0: PCI bridge, secondary bus 0001:81
pci 0001:80:00.0:   IO window: disabled
pci 0001:80:00.0:   MEM window: disabled
pci 0001:80:00.0:   PREFETCH window: disabled
...
bus: 81 index 0 mmio: [0xfffe0000-0xfffe0fff]
bus: 81 index 1 mmio: [0xeb8000000-0xeb80fffff]
bus: 81 index 2 mmio: [0x0-0x0]
bus: 81 index 3 mmio: [0x0-0x0]

lspci -v does not show the device.


The default end point design does have a prefetchable region and does
show up properly:

pci 0001:80:00.0: PCI bridge, secondary bus 0001:81
pci 0001:80:00.0:   IO window: disabled
pci 0001:80:00.0:   MEM window: 0x81000000-0x810fffff
pci 0001:80:00.0:   PREFETCH window: 0x00000080000000-0x00000080ffffff
...
bus: 81 index 0 mmio: [0xfffe0000-0xfffe0fff]
bus: 81 index 1 mmio: [0xe81000000-0xe810fffff]
bus: 81 index 2 mmio: [0xe80000000-0xe80ffffff]
bus: 81 index 3 mmio: [0x0-0x0]

Working and non-working behaviour is identical on 2.6.27.7 and today's
-next tree.

Full u-boot, kernel and lspci -v output attached. Also put online on:

http://www.sidebranch.com/leon/next_broken.txt
http://www.sidebranch.com/leon/next_works.txt

Any ideas why/where this might go wrong? I'm diving into the code now,
especially seeing why the memory behind the bridge was "disabled".

Regards,
-- 
Leon
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