[PATCH 2/2] talitos: Freescale integrated security engine (SEC) driver

Kim Phillips kim.phillips at freescale.com
Sat May 31 06:35:05 EST 2008


On Fri, 30 May 2008 15:19:43 -0500
Scott Wood <scottwood at freescale.com> wrote:

> Kim Phillips wrote:
> > On Fri, 30 May 2008 14:41:17 -0500
> > Scott Wood <scottwood at freescale.com> wrote:
> > 
> >> Kim Phillips wrote:
> >>> On Fri, 30 May 2008 22:09:04 +0400
> >>> Evgeniy Polyakov <johnpol at 2ka.mipt.ru> wrote:
> >>>> Don't you want to protect against simultaneous access to register space
> >>>> from different CPUs? Or it is single processor board only?
> >>> Doesn't linux mask the IRQ line for the interrupt currently being
> >>> serviced, and on all processors?
> >> Yes.  Could there be interference from non-interrupt driver code on 
> >> another cpu (or interrupted code), though?
> > 
> > not that I can see - the fetch fifo register writes are protected with
> > per-channel spinlocks.
> 
> But you don't take the spinlocks from the interrupt handler.

why can't fetch fifo registers be written the same time the ISR is
being accessed?

Kim



More information about the Linuxppc-dev mailing list