[PATCH 3/4 V4] Enable MSI support for MPC8610HPCD board
Jason.Jin at freescale.com
Wed May 21 13:29:19 EST 2008
> -----Original Message-----
> From: Kumar Gala [mailto:galak at kernel.crashing.org]
> Sent: Tuesday, May 20, 2008 9:24 PM
> To: Jin Zhengxiong
> Cc: linuxppc-dev at ozlabs.org
> Subject: Re: [PATCH 3/4 V4] Enable MSI support for MPC8610HPCD board
> > diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/
> > powerpc/platforms/86xx/mpc8610_hpcd.c
> > index dea1320..290d717 100644
> > --- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
> > +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
> > @@ -71,9 +71,13 @@ static void __init mpc86xx_hpcd_init_irq(void)
> > /* Alloc mpic structure and per isu has 16 INT entries. */
> > mpic1 = mpic_alloc(np, res.start,
> > MPIC_PRIMARY | MPIC_WANTS_RESET |
> > - 0, 256, " MPIC ");
> > + 64, 256, " MPIC ");
> > BUG_ON(mpic1 == NULL);
> > + mpic_assign_isu(mpic1, 0, res.start + 0x10000);
> > + mpic_assign_isu(mpic1, 1, res.start + 0x10800);
> > + mpic_assign_isu(mpic1, 2, res.start + 0x11600);
> > +
> I don't understand why you are breaking the interrupts up like this.
> If you leave as it was, the MSIs would start at hw irq 176
If the ISU size is 0, mpic will only initialize the interrupt source num
Feature Reporting Register(FRR), For 8610 it's 104, for 8572 it is 108,
As the address
space of the interrupt source configuration register is not
with ISU=0, actually only the 16 externel interrupts and 64 internal
interrupts were initialized.
the Messaging interrupts and MSI interrupts were not intialized.
With the original code. the Messaging interrupts would start at hwirq
176 and the MSIs would
start at hwirq 224.
By setting the ISU=64, the Messaging interrupts would start at 128 and
the MSIs start at 176.
And all the interrupt sources will be initialized.
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