[PATCH v3 3/3] [POWERPC] 40x/Book-E: Save/restore volatile exception registers

[Josh Boyer]

On Fri, 16 May 2008 14:08:00 -0500 (CDT)
Kumar Gala <galak at kernel.crashing.org> wrote:

> On machines with more than one exception level any system register that
> might be modified by the "normal" exception level needs to be saved and
> restored on taking a higher level exception.  We already are saving
> and restoring ESR and DEAR.
> 
> For critical level add SRR0/1.
> For debug level add CSRR0/1 and SRR0/1.
> For machine check level add DSRR0/1, CSRR0/1, and SRR0/1.
> 
> On FSL Book-E parts we always save/restore the MAS registers for critical,
> debug, and machine check level exceptions.  On 44x we always save/restore
> the MMUCR.
> 
> Additionally, we save and restore the ksp_limit since we have to adjust it
> for each exception level.
> 
> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
> ---

<snip>

> --- a/arch/powerpc/kernel/entry_32.S
> +++ b/arch/powerpc/kernel/entry_32.S

<snip>

> +#ifdef CONFIG_40x
>  	.globl	ret_from_crit_exc
>  ret_from_crit_exc:
> +	mfspr	r9,SPRN_SPRG3
	lis 	r10,saved_ksp_limit at ha;
	lwz	r10,saved_ksp_limit at l(r10);
	tovirt(r9,r9);
> +	stw	r10,KSP_LIMIT(r9)
	lis	r9, crit_srr0 at ha;
	lwz	r9, crit_srr0 at l(r9);
	lis	r10, crit_srr1 at ha;
	lwz	r10, crit_srr1 at l(r10);
> +	mtspr	SPRN_SRR0,r9;
> +	mtspr	SPRN_SRR1,r10;
>  	RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI)
> +#endif /* CONFIG_40x */

With the above changes, I no longer get kernel panics on returning from
critical exceptions.  Breakpoints and single stepping worked on my
405GP board.

Again, not stress tested but it's looking much better.

josh