Feedback requested on switching the exception wrapper used for the PMU interrupt on ppc64

[Corey J Ashford]

Hi Benjamin and Olaf,

Thanks for the suggestions.

Ideally, what I'm looking for is something that mimics the operation of
MASKABLE_EXCEPTION_PSERIES.
I've been looking at the kernel code (entry_64.S, exception.h, head_64.S)
but am finding it quite complicated and hard to follow, particularly in the
area of interrupt disabling wrt the soft and hard disable logic.

My initial thought is to do something like this in the beginning of my
perfmon2 interrupt handler:

void perfmon_pmu_int_handler(struct pt_regs *regs) {

      if (get_paca()->soft_enabled == 0) {
            /* disable hardware interrupts */
            get_paca()->hard_enabled = 0;
            regs->msr &= ^MSR_EE;
            return;
      }
...
}

Does this seem like it might work?

Thanks

Corey Ashford
Software Engineer
IBM Linux Technology Center, Linux Toolchain
Beaverton, OR
503-578-3507
cjashfor at us.ibm.com


Benjamin Herrenschmidt <benh at kernel.crashing.org> wrote on 05/14/2008
11:46:07 PM:

>
> On Tue, 2008-05-13 at 15:26 -0700, Corey Ashford wrote:
> > The perfmon2 code is available here:
> > http://sourceforge.net/project/showfiles.php?group_id=144822
> >
> > perfmon2's interrupt handler does have a single entry point.  Could I
> > somehow mimic what the MASKABLE_EXCEPTION_PSERIES macro does inside
> > of
> > the perfmon2 interrupt handler?  Are there examples of this I can look
> > at?
> >
> > That would give us the best of both worlds.
>
> You can definitely snapshot as many data as you can, and if interrupts
> are soft-disabled, just return to the caller, storing that snapshot in
> some per-cpu data structure.
>
> You can then add something to local_irq_restore() that checks whether
> some perfmon2 stuff happened and does the actual storing of the data
> that were previously collected.
>
> Cheers,
> Ben.
>
>
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