[PATCH] 4xx: Workaround for CHIP_11 Errata
sr at denx.de
Fri May 16 01:16:43 EST 2008
On Thursday 15 May 2008, Josh Boyer wrote:
> The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that
> causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction
> requests that cross the end-of-memory-range boundary. Since the DDR
> controller only returns the valid portion of a read request, the bridge
> will prevent other PLB masters from completing their transactions.
> This implements the recommended workaround for this errata for chips that
> use older versions of firmware that do not already handle it. The last
> 4KiB of memory are hidden from the kernel to prevent the problem
> transactions from occurring.
> Signed-off-by: Josh Boyer <jwboyer at linux.vnet.ibm.com>
Acked-by: Stefan Roese <sr at denx.de>
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