[PATCH] [POWERPC] Xilinx: add compatibility for IBM coreconnect busses.
dwg at au1.ibm.com
Thu May 8 13:30:06 EST 2008
On Wed, May 07, 2008 at 09:46:30PM -0500, Josh Boyer wrote:
> On Thu, 8 May 2008 10:18:50 +1000
> David Gibson <david at gibson.dropbear.id.au> wrote:
> > On Wed, May 07, 2008 at 01:47:31PM -0700, Stephen Neuendorffer wrote:
> > > The IBM coreconnect names are pretty well defined, it appears. In
> > > addition, the Xilinx versions of these IPs seem to be proliferating.
> > > Hence, in the future let's prefer to use the standard names. I've
> > > left the old names in for some backward compatibility for existing
> > > device trees.
> > >
> > > Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer at xilinx.com>
> > If you're talking about future trees, can't you just slap "simple-bus"
> > on them avoid this monster id table?
> What is that and how does it work?
ePAPR states that busses which cannot be probed as such (i.e. the
device tree is the only way to figure out what's on the bus) should
have "simple-bus" in their compatible property. You can then just add
simple-bus to the of_bus_ids list and avoid adding umpteen other things.
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
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