[PATCH 2/3] [POWERPC] Xilinx: of_serial support for Xilinx uart 16550.

[John Linn]

Thanks for all the input. I'd like to propose a solution hoping to
arrive at consensus.

We can define a "sparse16550" binding that uses reg-shift and reg-offset
properties in the device tree. 

It seems like this is a common variable on the 16550 so that others
could also use it.  I like it because it specifies the differences
clearly from a normal 16550 yet is flexible enough to handle some other
variations also.

Thanks,
John

-----Original Message-----
From: Sergei Shtylyov [mailto:sshtylyov at ru.mvista.com] 
Sent: Monday, March 24, 2008 11:04 AM
To: Sergei Shtylyov
Cc: Grant Likely; linuxppc-dev at ozlabs.org; Paul Mackerras; John Linn
Subject: Re: [PATCH 2/3] [POWERPC] Xilinx: of_serial support for Xilinx
uart 16550.

Hi, I wrote:

>    Oh, well... unfortunately, we can't use UPIO_MEM32 "register model"

> in 8250.c anyway since that makes use of readl()/writel() -- which
treat 
> the bus as bigendian on PPC... anyway, we would need at least a 

    I was going to write "as little-endian"... :-<

> "reg-size" property, if not new "compatible"...

WBR, Sergei