[PATCH 2/3] [POWERPC] Xilinx: of_serial support for Xilinx uart 16550.

[Sergei Shtylyov]

Grant Likely wrote:

>> >> > Personally, I'm not fond of this approach.  There is already some
>> >> > traction to using the reg-shift property to specify spacing, and I
>> >> > think it would be appropriate to also define a reg-offset property to
>> >> > handle the +3 offset and then let the xilinx 16550 nodes use those.

>> >> Why do we need a reg-offset property when we can just add the offset
>> >> to the appropriate word(s) in the reg property?
>
>> > Primarily because the device creates 32 byte registers starting at 0;
>> > but they are also big-endian byte accessible so a byte read at offset
>> > 8 also works.

>>    Probably I misunderstood you: does it give the same result as offset 11?

> er; typo; oops.  A 32 bit read add offset 0 is the same as a byte read
> at offset *3*.

    Oh, well... unfortunately, we can't use UPIO_MEM32 "register model" in 
8250.c anyway since that makes use of readl()/writel() -- which treat the bus 
as bigendian on PPC... anyway, we would need at least a "reg-size" property, 
if not new "compatible"...

>> > reg-offset seems to be a better description of the hardware to me.

>>    Have you considered using the existing "big-endian" property?

> No I haven't, but that would work too.  I'm happy with that if it
> works for you.  If the property was defined, then the byte offset to
> the first reg would be adjusted by 1^(reg-shift) - 1

    You don't mean "xor" by ^, do you? :-O
    In fact, it should be <<...

> Cheers,
> g.

WBR, Sergei