Trouble with SCC UART ports when moving from ppc to powerpc
Laurent Pinchart
laurentp at cse-semaphore.com
Mon Mar 10 23:17:01 EST 2008
On Friday 07 March 2008 17:21, Scott Wood wrote:
> On Fri, Mar 07, 2008 at 03:20:55PM +0100, Laurent Pinchart wrote:
> > The CPM dual port ram was defined in the device tree as follows (copied
> > from the MPC8272ADS board device tree).
> >
> > muram at 0 {
> > #address-cells = <1>;
> > #size-cells = <1>;
> > ranges = <0 0 10000>;
> >
> > data at 0 {
> > compatible = "fsl,cpm-muram-data";
> > reg = <0 2000 9800 800>;
> > };
> > };
> >
> > Changing the reg property to
> >
> > reg = <80 1f80 9800 800>;
> >
> > fixed my problem.
>
> Perhaps there's an SMC1 running with its parameter RAM at offset zero?
Good guess. U-Boot configured SMC1 with its parameter RAM at offset 0.
> > Does anyone have any clue regarding what could write to the dpram ? I
> > thought about some CPM peripheral set up by the boot loader, but my board
> > initialization code calls cpm2_reset() long before initializing SCC1.
>
> cpm2_reset() doesn't currently actually reset the CPM, for some reason
> (unlike cpm1). This should probably be fixed, though then we'd have to
> deal with assigning SMC parameter RAM addresses ourselves.
I had overlooked that. Resetting the CPM in cpm2_reset() helps. Is there any
reason not to rset the CPM in cpm2_reset() ?
How should SMC parameter RAM assignment be handled ? I'm not very familiar
with the CPM1, but for CPM2 the cpm_uart driver could easily cpm_dpalloc()
parameter RAM.
> For now, the above fix should be done on any board with an active SMC
> device (assuming SMC parameter RAM at zero, as u-boot sets it; other
> bootloaders may need to exempt a different region).
Thanks for your help.
Best regards,
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
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