[patch 9/9] powerpc/cell: Add DMA_ATTR_STRONG_ORDERING dma attribute and use in IOMMU code

[Roland Dreier]

Sorry for the late comments, I missed this when it went by before.

 > +DMA_ATTR_STRONG_ORDERING
 > +----------------------
 > +
 > +DMA_ATTR_STRONG_ORDERING specifies that previous reads and writes are
 > +performed in the order in which they're received by the IOMMU; thus
 > +reads and writes may not pass each other.

I don't understand what this is trying to say.  What is "previous"
referring to?  What does "received by the IOMMU" mean -- do you mean
issued onto the bus by the CPU? When you say "reads and writes may not
pass each other," do you mean just that reads may not pass writes and
writes may not pass reads, or do you mean that reads also can't pass
reads and writes can't pass writes?

Since I don't know exactly what this attribute does, I can't be sure,
but it seems that making weak ordering the default is dangerous in that
it breaks drivers that expect usual memory ordering semantics.  Would it
be safer/better to make strong ordering the default and then add a
"WEAK_ORDERING" attribute that drivers can use as an optimization?

 - R.