[PATCH] MPC52xx PCI write combine timer

[Grant Likely]

On Thu, Jul 10, 2008 at 11:53:16AM +0200, Andre Schwarz wrote:
> On MPC52xx the PCI target control register (PCITCR) @ MBAR + 0xD6C is initialized with
> only bit 7 (Latrule disable) set. The 8-Bit write combine timer (Bits 24..31) should be
> also set to a reasonable value _greater zero_ (0x08 = default) since setting it to 0x00
> leads to _very poor_ performance as a PCI target since external burst won't be possible
> at all.
> 
> Setting the WCT to 0x08 (cache-line size) leads to good overall perfomance.

Looks good to me.  I'll test it here and pick it up if all looks good.

Cheers,
g.