[PATCH2/2] [POWERPC] CPM1: implement GPIO LIB API on CPM1 Freescale SoC.

[Grant Likely]

On Tue, Jul 01, 2008 at 05:40:46PM +0200, Jochen Friedrich wrote:
> Hi Grant,
> 
> sorry for the late response on this one.
> 
> > 2. You need to specifiy exact chip names in your compatible string.
> > "fsl,cpm1-pario-<bank>" is a made up thing.
> 
> >>  +       for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank16")
> >>  +               cpm1_gpiochip_add16(np);
> >>  +
> >>  +       for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank32b")
> >>  +               cpm1_gpiochip_add32(np);
> >>  +
> >>  +       /* Port E uses CPM2 layout */
> >>  +       for_each_compatible_node(np, NULL, "fsl,cpm1-pario-bank32e")
> >>  +               cpm2_gpiochip_add32(np);
> 
> What do you suggest here?
> 
> All GPIO ports of CPM1/CPM2 are on the SoC, so the chip name is in fact the CPU itself
> (like fsl,mpc866-pario-bank16).

Right; so that is what I think you should call them. 'fsl,mpc866-*' instead
of 'fsl,cpm1-*'.  If multiple mpc8xx parts have the cpm1 core, then
choose one of the parts for all the others to claim compatibility with.

Now, there is a possible exception here... *IF* 'fsl,cpm1' is a very
well defined ASIC logic block that is known to be identical or versioned
between the various 8xx parts, *THEN* it is probably okay to call it
fsl,cpm1 and my previous comment does not apply.  But, I think it must
be documented in the device tree binding as to what it is and where to
get documentation for it.  And you should still have the first
compatible value to be something like "fsl,mpc866-pario-bank16",
followed by the cpm ones.

This was recently discussed between Kim and Segher.

g.