[RFC/PATCH 1/2] powerpc: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED

Trent Piepho tpiepho at freescale.com
Thu Dec 11 09:55:18 EST 2008

On Thu, 11 Dec 2008, Benjamin Herrenschmidt wrote:
> On Wed, 2008-12-10 at 11:33 -0800, Trent Piepho wrote:
>> On Wed, 10 Dec 2008, Benjamin Herrenschmidt wrote:
>>> This changes the logic so that instead, the PTE now contains
>>> _PAGE_COHERENT for all normal RAM pages tha have I = 0. The hash
>>> code clears it if the feature bit is not set.
>> Why not check the feature bit when the PTE is made and unset _PAGE_COHERENT
>> at that point?  In fact, could you do something like:
> Not sure what you mean. Inside set_pte_at ? Well, the one line of asm is
> going to be in the noise in the hash code, I'm just flipping an existing
> condition. I like the PTE to represent whether it's supposed to be a
> coherent page.

In the code that does the mapping.  It's a lot cheaper to figure out if
_PAGE_COHERENT is needed once per mapping instead of per page per fault.

It sounds like getting it right is a lot more complicated than just one
instruction.  No M bit for non-SMP, except for some 74xx, or if a MPC107
bridge is used, which should be determined at runtime.  And does the MPC107
thing apply to all pages or just those PCI memory behind the bridge?  Or

> I've been told that setting M on non-SMP will slows things down.  But
>> couldn't you just change _PAGE_BASE on non-SMP instead of clearning it in
>> the miss handler?
> Well, because we need it set on non SMP on some 74xx.. maybe we can
> have it set in PAGE_BASE only if CONFIG_SMP and CONFIG_6xx ?

That's what I was thinking, set it in page base for SMP and other instances
when we know it's necessary at compile time.  If/when there is a runtime
check, then it would be lot easier to put that check in the code that made
the mapping instead of the miss handler.

>> I have a patch to remove this IORESOURCE_PREFETCH hack.  The current kernel
>> creates two files, resourceN and resourceN_wc, for prefetchable BARs to
>> allow the user to choose what mode to use.
> Ah ? That's new ? I missed it. Has X been updated to use them ? If not,
> keep the hack for a little while more :-)

It's rather new so I bet X servers that use it aren't widely deployed yet.

commit 45aec1ae72fc592f231e9e73ed9ed4d10cfbc0b5
Author: venkatesh.pallipadi at intel.com <venkatesh.pallipadi at intel.com>
Date:   Tue Mar 18 17:00:22 2008 -0700

     x86: PAT export resource_wc in pci sysfs

Patch title is somewhat misleading, as it doesn't touch any x86 specific
code.  And people complain when I used booke instead of fsl-booke...  like
I want to make it any easier to have patches ignored.

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