[RFC/PATCH 1/2] powerpc: Rework usage of _PAGE_COHERENT/NO_CACHE/GUARDED

Trent Piepho tpiepho at freescale.com
Thu Dec 11 06:33:07 EST 2008


On Wed, 10 Dec 2008, Benjamin Herrenschmidt wrote:
> This changes the logic so that instead, the PTE now contains
> _PAGE_COHERENT for all normal RAM pages tha have I = 0. The hash
> code clears it if the feature bit is not set.

Why not check the feature bit when the PTE is made and unset _PAGE_COHERENT
at that point?  In fact, could you do something like:

#if defined(CONFIG_SMP) || ....
#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
#else
#define _PAGE_BASE	(_PAGE_PRESENT | _PAGE_ACCESSED)
#endif

> I haven't touched at the FSL BookE code yet. It may need to selectively
> clear M in the TLB miss handler ... or not. Depends what the impact of
> M on non-SMP E5xx setup is. I also didn't bother to clear it on 440 because
> it just has no effect (ie, it won't slow things down).

I've been told that setting M on non-SMP will slows things down.  But
couldn't you just change _PAGE_BASE on non-SMP instead of clearning it in
the miss handler?

> 	for_each_pci_dev(pdev) {
> 		for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
> 			struct resource *rp = &pdev->resource[i];
> @@ -422,14 +417,14 @@ pgprot_t pci_phys_mem_access_prot(struct
> 	}
> 	if (found) {
> 		if (found->flags & IORESOURCE_PREFETCH)
> -			prot &= ~_PAGE_GUARDED;
> +			prot = pgprot_noncached_wc(prot);
> 		pci_dev_put(pdev);
> 	}

I have a patch to remove this IORESOURCE_PREFETCH hack.  The current kernel
creates two files, resourceN and resourceN_wc, for prefetchable BARs to
allow the user to choose what mode to use.

Though I want to be able to map PCI resources as cached too.  I'm not sure
what a good way to add that is.  Yet another resource file?  The first
proposal for allowing WC mappings was to add support for ioctl() on sysfs
attributes.  Then one could use ioctl() after opening the resource file to
specify what mode to map it with.  No one liked ioctl(), but clearly the
current method doesn't scale well to all 32 combinations of the WIMGE bits.



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