[PATCH] powerpc: Fix bogus cache flushing on all 40x and BookE processors

[Trent Piepho]

On Tue, 2 Dec 2008, Benjamin Herrenschmidt wrote:
> On Tue, 2008-12-02 at 01:36 -0600, Kumar Gala wrote:
>
>>> #define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
>>> 	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
>>> -	    CPU_FTR_UNIFIED_ID_CACHE)
>>> +	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
>>> #define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
>>> -	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
>>> +	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP |
>>> CPU_FTR_NODSISRALIGN \
>>
>> Added a '|' at the end of the line before the escape
>
> Right. Will send a new patch tomorrow. Appart from that, have you
> verified it doesn't have any adverse effects for you ? I did some quick
> tests on 440 and things seem to be fine.


#ifdef __powerpc64__
#define LONG_ASM_CONST(x)               ASM_CONST(x)
#else
#define LONG_ASM_CONST(x)               0
#endif

#define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)

Am I not looking at the right code?  Since e200 and e500 aren't powerpc64,
doesn't adding CPU_FTR_NOEXECUTE have no effect at all?