[PATCH] powerpc: Fix determining TI_CPU in power_save_ppc32_restore()

[Kumar Gala]

The calculation to get TI_CPU based off of SPRG3 was just plain wrong.
Since we already have thread_info in r9 there is no reason to bother
to figure it out again.

This was pointed out by Chen Gong <G.Chen at freescale.com>

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---

Paul, this is in for-2.6.27 branch.

- k

 arch/powerpc/kernel/idle_6xx.S  |   13 +++++++------
 arch/powerpc/kernel/idle_e500.S |   11 ++++++-----
 2 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/kernel/idle_6xx.S b/arch/powerpc/kernel/idle_6xx.S
index 019b02d..0138d88 100644
--- a/arch/powerpc/kernel/idle_6xx.S
+++ b/arch/powerpc/kernel/idle_6xx.S
@@ -151,19 +151,20 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  * Return from NAP/DOZE mode, restore some CPU specific registers,
  * we are called with DR/IR still off and r2 containing physical
  * address of current.  R11 points to the exception frame (physical
- * address).  We have to preserve r10.
+ * address).  We have to preserve r10.  R9 contains the physical
+ * address of thread_info.
  */
 _GLOBAL(power_save_ppc32_restore)
-	lwz	r9,_LINK(r11)		/* interrupted in ppc6xx_idle: */
-	stw	r9,_NIP(r11)		/* make it do a blr */
-
 #ifdef CONFIG_SMP
-	mfspr	r12,SPRN_SPRG3
-	lwz	r11,TI_CPU(r12)		/* get cpu number * 4 */
+	lwz	r11,TI_CPU(r9)		/* get cpu number * 4 */
 	slwi	r11,r11,2
 #else
 	li	r11,0
 #endif
+
+	lwz	r9,_LINK(r11)		/* interrupted in ppc6xx_idle: */
+	stw	r9,_NIP(r11)		/* make it do a blr */
+
 	/* Todo make sure all these are in the same page
 	 * and load r11 (@ha part + CPU offset) only once
 	 */
diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S
index 0630403..c9d7234 100644
--- a/arch/powerpc/kernel/idle_e500.S
+++ b/arch/powerpc/kernel/idle_e500.S
@@ -76,18 +76,19 @@ END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
 /*
  * Return from NAP/DOZE mode, restore some CPU specific registers,
  * r2 containing physical address of current.
+ * r9 points to thread_info
  * r11 points to the exception frame (physical address).
  * We have to preserve r10.
  */
 _GLOBAL(power_save_ppc32_restore)
-	lwz	r9,_LINK(r11)		/* interrupted in e500_idle */
-	stw	r9,_NIP(r11)		/* make it do a blr */
-
 #ifdef CONFIG_SMP
-	mfspr	r12,SPRN_SPRG3
-	lwz	r11,TI_CPU(r12)		/* get cpu number * 4 */
+	lwz	r11,TI_CPU(r9)		/* get cpu number * 4 */
 	slwi	r11,r11,2
 #else
 	li	r11,0
 #endif
+
+	lwz	r9,_LINK(r11)		/* interrupted in e500_idle */
+	stw	r9,_NIP(r11)		/* make it do a blr */
+
 	b	transfer_to_handler_cont
-- 
1.5.5.1