[PATCH] powerpc: i2c-mpc: make speed registers configurable via FDT

[Jon Smirl]

On 7/31/08, Grant Likely <grant.likely at secretlab.ca> wrote:
> On Thu, Jul 31, 2008 at 03:37:07PM -0500, Timur Tabi wrote:
>  > Grant Likely wrote:
>  >
>  > > How is the divider controlled?  Is it a fixed property of the SoC?
>  >
>  > Yes.  The divider is either 1, 2, or 3, and the only way to know which one
>  > it is is to look up the specific SOC model number.  And depending on the
>  > SOC model, there may also be a register that needs to be looked up.
>  >
>  > > a
>  > > shared register setting? or a register setting within the i2c device?
>  >
>  > The I2C device itself has no idea what the divider is.  It only sees the
>  > result of the divider.
>
>
> Then that absolutely suggests to me that either the final clock or the
>  divider should be encoded in the i2c node; not in the soc node.

Isn't there a single global divider that generates all the i2c source
clocks? You don't want to copy a global value into each i2c node.
Aren't we talking about the /2 or /3 or /1 divider that appears to be
randomly implemented on various members of the mpc8xxx family?

>
>
>  g.
>


-- 
Jon Smirl
jonsmirl at gmail.com