[PATCH 2/2] PowerPC: Fix Sequoia MAL0 and EMAC dts entries.

Valentine Barshak vbarshak at ru.mvista.com
Wed Sep 19 21:14:00 EST 2007

David Gibson wrote:
> On Tue, Sep 18, 2007 at 09:29:13PM +0400, Valentine Barshak wrote:
>> According to PowerPC 440EPx documentation,
>> MAL0 is comprised of four channels (two transmit and two receive).
>> Each channel is dedicated to one of two EMAC cores.
>> This patch fixes Sequoia DTS MAL0 entry and EMAC entries,
>> assigning correct channel numbers to EMACs.
> Hrm.. did they change the EMAC in 440EPx to only use one MAL
> tx-channel?  All the older ones could use two (for no readily apparent
> reason, IMO).
Yes, they did.
Just 1 tx and 1 rx-channel per EMAC. Just 2 bits to select channels, 
while all other bits in MAL registers are reserved.
I'm not sure why they did it (possible bus bandwidth problems), but it's 
impossible to set more than 1 rx/tx channel for each EMAC in 440EPx.

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