[PATCH] [POWERPC] 85xx: Add basic Uniprocessor MPC8572 DS port

Kumar Gala galak at kernel.crashing.org
Fri Sep 14 07:23:50 EST 2007

On Sep 13, 2007, at 11:53 AM, Segher Boessenkool wrote:

>>> What is a "front side cache"?  What exactly does it cache?  If it's
>>> a cache for one CPU only, that fact should be shown in the device
>>> tree somehow.
>> Its in front of the memory controllers.  Its not specific to a  
>> given CPU.
> Ah, I see.  That relationship is implicit in the device tree already,
> both this cache controller and that memory controller are child nodes
> of the same soc node, so your device tree is fine.
> Just for my own understanding, is this a coherent cache?  (I'm too
> lazy to read the manual ;-) )

yes its coherent.  Our caches tend to be coherent.

- k

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