[PATCH 5/5] Add DMA engine driver for Freescale MPC85xx processors.

[Zhang Wei-r63237]

Hi, 
> --- /dev/null
> > +++ b/drivers/dma/fsldma.c
> > @@ -0,0 +1,995 @@
> 
> Thanks for using kernel-doc notation.  However, ...
> 
> > +/**
> > + * fsl_dma_alloc_descriptor - Allocate descriptor from 
> channel's DMA pool.
> 
> Function parameters need to be listed & described here.
> See Documentation/kernel-doc-nano-HOWTO.txt or other source files
> for examples.
> 
> (Applies to all documented function interfaces here.)

All right, I'll add full descriptions here. :P

> 
> > + *
> > + * Return - The descriptor allocated. NULL for failed.
> > + */
> > +static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
> > +					struct fsl_dma_chan *fsl_chan,
> > +					gfp_t flags)
> > +{
> ...
> > +}
> 
> > +/**
> > + * fsl_chan_xfer_ld_queue -- Transfer the link descriptors 
> in channel
> > + *                           ld_queue.
> 
> The function's "short description" (unfortunately) must be on only one
> line.  E.g.:
> 
>  * fsl_chan_xfer_ld_queue - Transfer link descriptors in 
> channel ld_queue.
> 

How about it's length greater than 80?

> > + */
> > +static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan)
> > +{
> ...
> > +}
> 
> > diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
> > new file mode 100644
> > index 0000000..05be9ed
> > --- /dev/null
> > +++ b/drivers/dma/fsldma.h
> > @@ -0,0 +1,188 @@
> > +struct fsl_dma_chan_regs {
> > +	__mix32	mr;		/* 0x00 - Mode Register */
> > +	__mix32	sr;		/* 0x04 - Status Register */
> > +	__mix64	cdar;		/* 0x08 - Cureent descriptor 
> address register */
> 
>                                           Current
> 

I'll fix it.

Thanks!
- zw