[PATCH 08/10] bootwrapper: Add a firmware-independent "raw" target.

[Segher Boessenkool]

>>> +static inline void disable_irq(void)
>>> +{
>>> +       int dummy;
>>> +       asm volatile("mfmsr %0; rlwinm %0, %0, 0, ~(1<<15); mtmsr %0"
>>> :
>>> +                    "=r" (dummy) : : "memory");
>>> +}
>
> This will fail (mtmsr illegal instruction) on 64 bit processors that do
> not implement the bridge facility (POWER4, 5, 6, PPC970, ...)

The latest ISA lists mtmsr as non-optional, not part of the bridge
facility.  That suggests that all CPUs do in fact implement it.

970 does implement the 64-bit bridge facility, btw (well, "most of it").


Segher