[PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.
dan at embeddedalley.com
Thu Sep 6 08:27:31 EST 2007
On Sep 5, 2007, at 1:59 PM, Scott Wood wrote:
> BTW, it seems I misremembered what the conflict was -- it's not with
> ioremap space, but with the default location of the consistent memory
> pool (at 0xff100000).
Change the configuration option to move this somewhere
else, outside of the wired mapping.
As I said in the last message, these lower end processors
are very resource challenged, and we need to clever
about the memory mapping and use of the TLBs. This
isn't a place to be creating fancy memory maps and
algorithms to manage them. Use maximum mappings
whenever possible, configure the memory controller
to pack as much stuff into this single TLB mapping
as possible. Something configurable like this memory
pool should not be a reason to give up these performance
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