[PATCH 1/9] 8xx: Fix CONFIG_PIN_TLB.

[Dan Malek]

On Sep 5, 2007, at 1:53 PM, Scott Wood wrote:

> Where is the code that checks for pinned TLB entries on 8xx when doing
> ioremap?

I don't know.  I haven't been the maintainer for the 2.6
changes.

>   Why could this not be done with a 512K mapping?  How was this
> even tested, given the obvious wrong-register mistake in the other
> CONFIG_PIN_TLB section?  On what do you base the assumption that  
> flash is
> within 8MB of the IMMR base?

All of this worked in 2.4, many changes were part
of the evolution in 2.6...  configurable pinned entries,
large page sizes, variations, I didn't keep track of
all of this.  I just assumed I'd have to fix it all if I
ever needed to use it, which I haven't.  The original
version of 8xx could wire exactly three entries for
8M text, 8M data, and 8M IMMR plus upper device
addresses.  We would set the IMMR to ff800000,
cover the CPM, some other devices and the flash
at the top of memory.  If you have too much flash, this
had to be adjusted accordingly, but for small systems
this was a nice performance enhancement.

> I didn't change it on a whim, I changed it because ioremap() wasn't
> working the way it currently is.

This processor is severely resource limited.  It's
far better to fix ioremap and take advantage of this
performance enhancement than to further
cripple it.  Just like other processors test for
mapping by BATs or CAMs, the 8xx and
probably 4xx should test for wired mapping.

Unfortunately, lots of things got messed up on 2.6
for the 8xx.  I was not in the loop to approve changes,
and most of my advice was ignored. :-)

Thanks.

	-- Dan