[PATCH v7 3/3] [POWERPC] MPC832x_RDB: update dts to use SPI1in QE, register mmc_spi stub
timur at freescale.com
Mon Sep 3 23:55:56 EST 2007
Segher Boessenkool wrote:
> Not at all. The device tree describe how the hardware _is_
> set up (after firmware, bootloader etc.); now how it _should
> be_ set up by the kernel.
I agree with this general sentiment, but in the case of QE pin configuration,
then device tree, in a sense, does contain how the hardware is set up. The
par_io section in the device tree describes they layout of the wiring between
the SOC and peripherals. If the par_io registers are not programmed
correctly, the SOC won't be able to communicate with the peripheral.
Sure, the kernel currently reads the device tree and programs the par_io
registers accordingly, but that doesn't mean the information *shouldn't* be in
the device tree.
> It would make a lot of sense to do this work in the firmware
> instead, but it doesn't make sense at all to put this stuff
> into the device tree.
1) If the firmware does configure the pins, then the device tree *will*
describe how the hardware is set up.
2) How would the firmware know how to do board configuration if it doesn't
have the instructions in the device tree?
Besides, every other board does it's par_io configuration based on the device
tree. So if Anton is going to break that pattern, we should be talking about
moving all that code into U-boot, instead of just putting in a one-time
exception (especially since the patch contains no explanation as to why these
par_io pins are being configured differently than every other board).
Linux Kernel Developer @ Freescale
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