[microblaze-uclinux] RE: [PATCH v3] Device tree bindings for Xilinx devices
Stephen Neuendorffer
stephen.neuendorffer at xilinx.com
Wed Oct 24 11:15:22 EST 2007
I've incorporated a good portion of the combined feedback and pushed the
gen_mhs_devtree patches back to Grant.
The few things I haven't done are relatively cosmetic (like getting rid
of linux,phandle references, decimal vs. hex, and the 'embedded \0')
,
The one significant problem that I'm not sure how to deal with pertains
to multiple memory nodes, which often happens. Should they all be
exported at the toplevel (which dtc seems to require), or only the main
memory which is used by Linux?
Some specific responses below:
>>
>> Steve
>>
>> / {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "ibm,plb4";
>Not quite; the bus itself needs to be one level deeper. Compatible
>here is refering to the platform itself, not the bus and so should be
>the actual board name or something similar. Maybe something like:
>"xlnx,ml403","xlnx,generic-virtex4";
perhaps the toplevel compatible node should contain a SHA1 hash of
system.mhs?
>> Ethernet_MAC {
>> compatible =
>> "xilinx,opb-ethernet-1.04.a\0xilinx,opb-ethernet";
>
>Yes; this is the idea; but I don't like "xilinx,opb-ethernet". I
>think we should always specify specific versions and not try to guess
>what the 'generic' device compatible interface is.
I've left this in, until we can come up with canonical compatible
versions.
(perhaps just truncating the minor version?)
I've attached one more generated test tree, in the hopes that
gen-mhs-devtree can be put to bed and used to validate Michel's BSP
oriented version. Again, the goal is not to make it perfect, but to
make it good enough that it can be a temporary bridge between the
EDK-integrated generator and those writing device drivers.
Steve
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "system.mhs";
chosen {
bootargs = "root=/dev/xsysace/disc0/part2";
interrupt-controller = <101>;
} ;
cpus {
#address-cells = <1>;
#cpus = <1>;
#size-cells = <0>;
microblaze,6.00.b at 0 {
32-bit;
clock-frequency = <5f5e1000>;
d-cache-line-size = <10>;
d-cache-size = <4000>;
device_type = "cpu";
i-cache-line-size = <10>;
i-cache-size = <4000>;
linux,boot-cpu;
reg = <0>;
timebase-frequency = <1fca055>;
xlnx,cache-byte-size = <4000>;
xlnx,dcache-baseaddr = <50000000>;
xlnx,dcache-byte-size = <4000>;
xlnx,dcache-highaddr = <5fffffff>;
xlnx,debug-enabled = <1>;
xlnx,div-zero-exception = <1>;
xlnx,dopb-bus-exception = <1>;
xlnx,fpu-exception = <1>;
xlnx,icache-baseaddr = <50000000>;
xlnx,icache-highaddr = <5fffffff>;
xlnx,ill-opcode-exception = <1>;
xlnx,iopb-bus-exception = <1>;
xlnx,number-of-pc-brk = <2>;
xlnx,pvr = <2>;
xlnx,unaligned-exceptions = <1>;
xlnx,use-barrel = <1>;
xlnx,use-dcache = <1>;
xlnx,use-div = <1>;
xlnx,use-fpu = <1>;
xlnx,use-icache = <1>;
xlnx,use-msr-instr = <1>;
xlnx,use-pcmp-instr = <1>;
} ;
} ;
memory {
device_type = "memory";
reg = < 50000000 10000000 >;
} ;
opb_v20 {
compatible =
"xlnx,opb-v20-1.10.c\0xlnx,opb-v20\0ibm,opb";
ethernet at 40c00000 {
compatible =
"xlnx,opb-ethernet-1.04.a\0xlnx,opb-ethernet";
device_type = "network";
interrupt-parent = <101>;
interrupts = < 1 0 >;
reg = < 40c00000 10000 >;
xlnx,cam-exist = <0>;
xlnx,dev-blk-id = <0>;
xlnx,dev-mir-enable = <0>;
xlnx,dma-present = <1>;
xlnx,edk-name = "Ethernet_MAC";
xlnx,include-dev-pencoder = <0>;
xlnx,ipif-rdfifo-depth = <4000>;
xlnx,ipif-wrfifo-depth = <4000>;
xlnx,jumbo-exist = <0>;
xlnx,mac-fifo-depth = <10>;
xlnx,mii-exist = <1>;
xlnx,opb-clk-period-ps = <2710>;
xlnx,reset-present = <1>;
xlnx,rx-dre-type = <0>;
xlnx,rx-include-csum = <0>;
xlnx,tx-dre-type = <0>;
xlnx,tx-include-csum = <0>;
} ;
interrupt-controller at 41200000 {
#interrupt-cells = <2>;
compatible =
"xlnx,opb-intc-1.00.c\0xlnx,opb-intc";
interrupt-controller;
linux,phandle = <101>;
reg = < 41200000 10000 >;
xlnx,edk-name = "opb_intc_0";
} ;
memory at 50000000 {
compatible =
"xlnx,mch-opb-ddr2-1.02.a\0xlnx,mch-opb-ddr2";
device_type = "memory";
reg = < 50000000 10000000 >;
xlnx,ddr-async-support = <1>;
xlnx,ddr-awidth = <d>;
xlnx,ddr-bank-awidth = <2>;
xlnx,ddr-cas-lat = <3>;
xlnx,ddr-col-awidth = <a>;
xlnx,ddr-dwidth = <20>;
xlnx,ddr-tfaw = <c350>;
xlnx,ddr-tmrd = <61a8>;
xlnx,ddr-tras = <15f90>;
xlnx,ddr-trc = <fde8>;
xlnx,ddr-trcd = <61a8>;
xlnx,ddr-trefi = <7704c0>;
xlnx,ddr-trfc = <1c138>;
xlnx,ddr-trp = <4e20>;
xlnx,ddr-trrd = <3a98>;
xlnx,ddr-twr = <3a98>;
xlnx,ddr-twtr = <1>;
xlnx,edk-name = "DDR2_SDRAM_32Mx32";
xlnx,extra-tsu = <0>;
xlnx,idelayctrl-loc =
"IDELAYCTRL_X0Y5-IDELAYCTRL_X0Y4-IDELAYCTRL_X0Y1-IDELAYCTRL_X0Y0";
xlnx,include-opb-burst-support = <1>;
xlnx,include-opb-ipif = <1>;
xlnx,mch0-accessbuf-depth = <4>;
xlnx,mch1-accessbuf-depth = <8>;
xlnx,num-banks-mem = <1>;
xlnx,num-channels = <2>;
xlnx,num-clk-pairs = <2>;
xlnx,num-idelayctrl = <4>;
xlnx,reg-dimm = <0>;
xlnx,xcl0-writexfer = <0>;
} ;
opb_hwicap at 41300000 {
compatible =
"xlnx,opb-hwicap-1.10.a\0xlnx,opb-hwicap";
reg = < 41300000 10000 >;
xlnx,edk-name = "opb_hwicap_0";
} ;
opb_iic at 40800000 {
compatible =
"xlnx,opb-iic-1.02.a\0xlnx,opb-iic";
interrupt-parent = <101>;
interrupts = < 2 0 >;
reg = < 40800000 10000 >;
xlnx,clk-freq = <5f5e100>;
xlnx,edk-name = "IIC_EEPROM";
xlnx,iic-freq = <186a0>;
xlnx,ten-bit-adr = <0>;
} ;
opb_mdm at 41400000 {
compatible =
"xlnx,opb-mdm-2.00.a\0xlnx,opb-mdm";
reg = < 41400000 10000 >;
xlnx,edk-name = "debug_module";
xlnx,mb-dbg-ports = <1>;
xlnx,uart-width = <8>;
xlnx,use-uart = <1>;
} ;
opb_timer at 41c00000 {
compatible =
"xlnx,opb-timer-1.00.b\0xlnx,opb-timer";
interrupt-parent = <101>;
interrupts = < 0 0 >;
reg = < 41c00000 10000 >;
xlnx,count-width = <20>;
xlnx,edk-name = "opb_timer_1";
xlnx,one-timer-only = <1>;
} ;
serial at 40600000 {
compatible =
"xlnx,opb-uartlite-1.00.b\0xlnx,opb-uartlite";
device_type = "serial";
interrupt-parent = <101>;
interrupts = < 3 0 >;
reg = < 40600000 10000 >;
xlnx,baudrate = <2580>;
xlnx,clk-freq = <5f5e100>;
xlnx,data-bits = <8>;
xlnx,edk-name = "RS232_Uart_1";
xlnx,odd-parity = <0>;
xlnx,use-parity = <0>;
} ;
} ;
} ;
> -----Original Message-----
> From: owner-microblaze-uclinux at itee.uq.edu.au
> [mailto:owner-microblaze-uclinux at itee.uq.edu.au] On Behalf Of
> Stephen Neuendorffer
> Sent: Friday, October 19, 2007 4:43 PM
> To: Stephen Neuendorffer; Grant Likely
> Cc: Leonid; Arnd Bergmann; microblaze-uclinux at itee.uq.edu.au;
> linuxppc-dev at ozlabs.org; Wolfgang Reissnegger
> Subject: [microblaze-uclinux] RE: [PATCH v3] Device tree
> bindings for Xilinx devices
>
>
> Here's a full .dts generated using an updated version of
> gen_mhs_devtree.py, following the proposal.
> It happens to be a microblaze system, but you get the idea.
>
> Grant: Is this pretty what you intend?
>
> Steve
>
> / {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "ibm,plb4";
> model = "system.mhs";
> Ethernet_MAC {
> compatible =
> "xilinx,opb-ethernet-1.04.a\0xilinx,opb-ethernet";
> device_type = "opb_ethernet";
> interrupt-parent = <101>;
> interrupts = < 1 0 >;
> reg = < 40c00000 10000 >;
> xilinx,cam-exist = <0>;
> xilinx,dev-blk-id = <0>;
> xilinx,dev-mir-enable = <0>;
> xilinx,dma-present = <1>;
> xilinx,include-dev-pencoder = <0>;
> xilinx,ipif-rdfifo-depth = <4000>;
> xilinx,ipif-wrfifo-depth = <4000>;
> xilinx,jumbo-exist = <0>;
> xilinx,mac-fifo-depth = <10>;
> xilinx,mii-exist = <1>;
> xilinx,opb-clk-period-ps = <2710>;
> xilinx,reset-present = <1>;
> xilinx,rx-dre-type = <0>;
> xilinx,rx-include-csum = <0>;
> xilinx,tx-dre-type = <0>;
> xilinx,tx-include-csum = <0>;
> } ;
> IIC_EEPROM {
> compatible = "xilinx,opb-iic-1.02.a\0xilinx,opb-iic";
> device_type = "opb_iic";
> interrupt-parent = <101>;
> interrupts = < 2 0 >;
> reg = < 40800000 10000 >;
> xilinx,clk-freq = <5f5e100>;
> xilinx,iic-freq = <186a0>;
> xilinx,ten-bit-adr = <0>;
> } ;
> RS232_Uart_1 {
> compatible =
> "xilinx,opb-uartlite-1.00.b\0xilinx,opb-uartlite";
> device_type = "opb_uartlite";
> interrupt-parent = <101>;
> interrupts = < 3 0 >;
> reg = < 40600000 10000 >;
> xilinx,baudrate = <2580>;
> xilinx,clk-freq = <5f5e100>;
> xilinx,data-bits = <8>;
> xilinx,odd-parity = <0>;
> xilinx,use-parity = <0>;
> } ;
> chosen {
> bootargs = "root=/dev/xsysace/disc0/part2";
> interrupt-controller = <101>;
> linux,platform = <600>;
> } ;
> cpus {
> #address-cells = <1>;
> #cpus = <1>;
> #size-cells = <0>;
> microblaze_0,6.00. {
> 32-bit;
> clock-frequency = <5f5e1000>;
> d-cache-line-size = <10>;
> d-cache-size = <4000>;
> device_type = "cpu";
> i-cache-line-size = <10>;
> i-cache-size = <4000>;
> linux,boot-cpu;
> reg = <0>;
> timebase-frequency = <1fca055>;
> xilinx,cache-byte-size = <4000>;
> xilinx,dcache-baseaddr = <50000000>;
> xilinx,dcache-byte-size = <4000>;
> xilinx,dcache-highaddr = <5fffffff>;
> xilinx,debug-enabled = <1>;
> xilinx,div-zero-exception = <1>;
> xilinx,dopb-bus-exception = <1>;
> xilinx,fpu-exception = <1>;
> xilinx,icache-baseaddr = <50000000>;
> xilinx,icache-highaddr = <5fffffff>;
> xilinx,ill-opcode-exception = <1>;
> xilinx,iopb-bus-exception = <1>;
> xilinx,number-of-pc-brk = <2>;
> xilinx,pvr = <2>;
> xilinx,unaligned-exceptions = <1>;
> xilinx,use-barrel = <1>;
> xilinx,use-dcache = <1>;
> xilinx,use-div = <1>;
> xilinx,use-fpu = <1>;
> xilinx,use-icache = <1>;
> xilinx,use-msr-instr = <1>;
> xilinx,use-pcmp-instr = <1>;
> } ;
> } ;
> debug_module {
> compatible = "xilinx,opb-mdm-2.00.a\0xilinx,opb-mdm";
> device_type = "opb_mdm";
> reg = < 41400000 10000 >;
> xilinx,mb-dbg-ports = <1>;
> xilinx,uart-width = <8>;
> xilinx,use-uart = <1>;
> } ;
> memory at 50000000 {
> device_type = "memory";
> edk_name = "DDR2_SDRAM_32Mx32";
> memreg:reg = < 50000000 10000000 >;
> } ;
> opb_hwicap_0 {
> compatible =
> "xilinx,opb-hwicap-1.10.a\0xilinx,opb-hwicap";
> device_type = "opb_hwicap";
> reg = < 41300000 10000 >;
> } ;
> opb_intc_0 {
> #interrupt-cells = <2>;
> compatible = "xilinx,opb-intc-1.00.c\0xilinx,opb-intc";
> device_type = "opb_intc";
> interrupt-controller;
> linux,phandle = <101>;
> reg = < 41200000 10000 >;
> } ;
> opb_timer_1 {
> compatible =
> "xilinx,opb-timer-1.00.b\0xilinx,opb-timer";
> device_type = "opb_timer";
> interrupt-parent = <101>;
> interrupts = < 0 0 >;
> reg = < 41c00000 10000 >;
> xilinx,count-width = <20>;
> xilinx,one-timer-only = <1>;
> } ;
> } ;
>
>
>
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