[PATCH 1/2] [PPC 4xx] invalidate_l2cache_range() implementation for ppc44x
yur at emcraft.com
Thu Nov 8 10:10:03 EST 2007
Thanks a lot for the feedbacks. Comments below.
On 07.11.2007, 7:04:28 you wrote:
> Some comments below. In general this patch adds #ifdefs in common code,
> that's normally frowned upon.
> It would maybe be better to add a new call to ppc_machdeps and call it
> if set.
Agree; this looks better indeed.
> On Wed, Nov 07, 2007 at 01:40:28AM +0300, Yuri Tikhonov wrote:
>> * Write any modified data cache blocks out to memory.
>> * Does not invalidate the corresponding cache lines (especially for
>> diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
>> index 5350704..8a2f9e6 100644
>> --- a/include/asm-powerpc/cache.h
>> +++ b/include/asm-powerpc/cache.h
>> @@ -10,12 +10,14 @@
>> #define MAX_COPY_PREFETCH 1
>> #elif defined(CONFIG_PPC32)
>> #define L1_CACHE_SHIFT 5
>> +#define L2_CACHE_SHIFT 5
>> #define MAX_COPY_PREFETCH 4
>> #else /* CONFIG_PPC64 */
>> #define L1_CACHE_SHIFT 7
>> #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
>> +#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)
> The above looks highly system dependent to me. Should maybe be a part
> of the cache info structures instead, and filled in from the device tree?
This is the Level-2 cache line parameter. I'll see what can be made here. For now I've just renamed these definitions and moved them into the PPC44x-specific header.
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com
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