[patch 4/4] powerpc 2.6.21-rt1: reduce scheduling latency by changing tlb flush size

[Tsutomu OWA]

At Mon, 14 May 2007 08:51:46 +0200, Thomas Gleixner wrote:

> On Mon, 2007-05-14 at 15:38 +0900, Tsutomu OWA wrote:
> > As I don't know how long it takes on other platforms, it would be better to 
> > enclose it within #ifdef CONFIG_PPC_CELLEB.
> 
> Yes, that might be appropriate. Can you add this and resend please ?

  Certainly, and thanks for your comment.

To reduce scheduling latecy by changing tlb flush size to 1.
Since tlb flush on Celleb is done by calling (an) expensive hypervisor call(s), 
it takes a long time to flush tlbs and causes scheduing latency.

Signed-off-by: Tsutomu OWA <tsutomu.owa at toshiba.co.jp>
-- owa

--- linux-2.6.21-rt1/include/asm-powerpc/tlbflush.h	2007-04-26 12:08:32.000000000 +0900
+++ rt/include/asm-powerpc/tlbflush.h	2007-05-14 16:12:47.000000000 +0900
@@ -25,7 +25,12 @@ struct mm_struct;
 #include <linux/percpu.h>
 #include <asm/page.h>
 
+#if defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT)
+/* Since tlb flush takes long time on Celleb, reduce it to 1 when Celleb && RT */
+#define PPC64_TLB_BATCH_NR 1
+#else
 #define PPC64_TLB_BATCH_NR 192
+#endif /* defined(CONFIG_PPC_CELLEB) && defined(CONFIG_PREEMPT_RT) */
 
 struct ppc64_tlb_batch {
 	unsigned long index;