MPC83xx SDMR setup error

[Kumar Gala]

On Mar 22, 2007, at 9:30 AM, Chuck Meade wrote:

> There appears to be an error in the MPC83xx SDMR setup in
> arch/powerpc/sysdev/qe_lib/qe.c line 259.  Since 0x1 shifted right  
> 13 bits
> (QE_SDMR_CEN_SHIFT) will always be zero, the CEN field will be set to
> zero.  This means the SDMR buffer size will always be 512, rather than
> the intended (and allocated) 1024 bytes.

What does this effect?  I agree the code is wrong.

> In addition, and not shown in the patch below, there is a conflict  
> in the
> alignment requirement for the value to be written to the SDEBCR  
> register.
> The SDEBCR holds the address in MURAM of the buffer to be used by  
> the SDMA
> controller.  In the MPC8323ERM.pdf section 18.1.7 titled "SDMA  
> Internal
> Resource", it states that "the base address must be aligned to a  
> 4KByte
> boundary."  However, later in the description of the SDEBCR in section
> 18.1.8.9, it states that the address must be "64 bytes aligned".   
> The code
> in arch/powerpc/sysdev/qe_lib/qe.c (line 254) that allocates this  
> buffer
> aligns it to a 64-byte boundary.  This is only correct if the  
> manual section
> 18.1.7, which requires a 4KByte alignment, is wrong.  Which manual  
> section
> is correct?

Hopefully someone at freescale will know.  I'd suggest possibly  
posting a support request to them to see if you can get a  
clarification since their UM is not self-consistent on the details.

> Chuck
>
> --- a/linux-2.6/arch/powerpc/sysdev/qe_lib/qe.c	2007-01-13  
> 09:37:03.000000000 -0500
> +++ b/linux-2.6/arch/powerpc/sysdev/qe_lib/qe.c	2007-03-22  
> 09:48:46.000000000 -0400
> @@ -256,7 +256,7 @@ static int qe_sdma_init(void)
>   		return -ENOMEM;
>
>   	out_be32(&sdma->sdebcr, sdma_buf_offset & QE_SDEBCR_BA_MASK);
> -	out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | (0x1 >>
> +	out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK | (0x1 <<
>   					QE_SDMR_CEN_SHIFT)));
>
>   	return 0;
>
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