83xx GPIO/EXT int in arch/powerpc/

[Marc Leeman]

> Are you comparing 8245 on arch=ppc to 83xx on arch=powerpc or 83xx in  
> both cases?

No, I'm comparing ARCH=ppc and ARCH=powerpc, both on 8347E. The
comparison with a 8245 is due to the fact that this 83xx platform is a
follow up of the 8245 design.

With the 8245, we got almost a doubling of the effective processing of
data through the network by replacing the eepro100 driver with the e100
driver from intel. Since data transfer rate from the network on a 83xx
seems to be slower than the 8245/e100 combination, there might be some
driver work to do too to get the same improvement; but that's currently
just speculation on my part; I hope to have a look into that after the
summer.

> Hmm, we really need to put SVR in there as well (add that to the todo  
> list).  Which 83xx is this?

MPC8347E

> Do you sense of how many calls you make to _hpi_set_hhwil &  
> __hpi_read_hpid?

We're using a couple of GPIOs to toggle the first halfword and the
second halfword (running HPI 16-bit). Since we only have implemented
single beat accesses in the UPM, we also need to toggle between address
and data.

For every word, there are 4 similar calls; a DSP binary that is loaded
over HPI is around 400 kB, so in 500,000 order of magnitude per DSP
binary load.

During operation, HPI is used to get info from the DSPs @100-120 times per
second; just a couple of bytes though.

> I think I know why the ppc case was more efficient.

Wheee.

probably the ioremap and iounmap have something to do with it; in the
debugging version of the code, this was done for every GPIO access (cf.
supra) and there the slow down was from 3-4 secs to 1-2 mins.

> >Even after this change; the load of a streaming application was
> >something of 40% on ppc and 60% on powerpc.
> 
> What's going on during the streaming?

Data is retreived from the network (UDP, TCP, mostly UDP/multicast
though) and partially decoded (converted to elementary stream). Data is
then transferred through an FPGA (over PCI) to a DSP with DMA (pushed
from the 83xx processor). The data is mapped from userspace into kernel
in blocks of 4096kB to avoid copying.

The transfer of data is pretty straighforward:
  1. map user page into kernel
  2. grab dma channel
  3. init dma channel
  4. dma data out
  5. wait for interrupt

-- 
  greetz, marc
You'll be happy to know I have a plan.
	Crichton - Through the Looking Glass
chiana 2.6.18-4-ixp4xx #1 Tue Mar 27 18:01:56 BST 2007 GNU/Linux
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