83xx GPIO/EXT int in arch/powerpc/

Marc Leeman marc.leeman at gmail.com
Tue Jun 12 02:21:35 EST 2007


> > Poor guy trying to figure out the right way to do
> > his stuff will run away screaming and go back hard coding his number in
> > his platform code before we are finished :-)
> 
> Heh I hope not.

Hm, I guess I took the dirty way suggested by Benjamin and having a look
at the CDS Freescale platform by copying the following in my platform
file:

static void __init mpc83xx_svc2_pcibios_fixup(void)
{
	struct pci_dev *dev;

	if ((dev = pci_get_device(VENDOR_ID_ALTERA,
					DEVICE_ID_FPGA834XG1, NULL))) {
		dev->irq = 23;
		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 23);
		pci_dev_put(dev);
	}

	/* Now map all the PCI irqs */
	dev = NULL;
	for_each_pci_dev(dev)
		pci_read_irq_line(dev);

}

I am planning to have another look at the proper (tm) way to fix it, by
experimenting with my dts file; but since I need to get a number of
boards released, it's a bit pushed backwards.


What is more disturbing though, is that a number of operations on the
powerpc arch seems significantly slower wrt the ppc arch.

ioremap and iounmap being the most important one: we are using a small
driver that uses one of the UPMs in combination with GPIOs for HPI (Host
Port Interface) for TI DSPs.

Where the loading of a DSP took only 3 seconds, it went up to over a
minute on powerpc (same driver code).

Changing the driver to ioremap and unmap 0xe2400000 only once at driver
initialisation and unloading (not really relevant on this embedded
system, shame on me) instead twice for every word greatly improves the
time (around one second). However, this optimisation has the same effect
on ppc too :-/

Running the same application with the same modules on ppc and powerpc
(transferring data from the network to an FPGA) has a 50% higher load on
powerpc. The transfer is done with mapping user pages into the kernel
and DMA'ing them over PCI. What all driver have in common is that there
are quite some writes/reads to the IMMR configuration.

Decreasing the read and writes to the LBC for HPI (0xe2400000) seems to
improve the overall load.

So my question would be if I need to specify a special section in the
dts file for some reason; next to the U-Boot configuration that sends
writes to this address through the UPMB?

If not, is there any other reason that might account for these
significant performance drops?

-- 
  greetz, marc
Aeryn, did I say or do anything to piss you off? I mean other than
caving in the side of your head?
	Crichton - Die Me, Dichotomy
chiana 2.6.18-4-ixp4xx #1 Tue Mar 27 18:01:56 BST 2007 GNU/Linux
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