[PATCH] Add the support of ST M48T59 RTC chip in rtc-class driver subsystem
Milton Miller
miltonm at bga.com
Tue Jun 12 00:35:42 EST 2007
On Mon Jun 11 17:56:40 EST 2007, Mark Zhan wrote:
> Add the support of ST M48T59 RTC chip driver in RTC class subsystem for
> Wind River SBC PowerQUICCII 82xx board
...
> +#define M48T59_CNTL 0x1ff8
> +#define M48T59_WATCHDOG 0x1ff7
> +#define M48T59_INTR 0x1ff6
> +#define M48T59_ALARM_DATE 0x1ff5
> +#define M48T59_ALARM_HOUR 0x1ff4
> +#define M48T59_ALARM_MIN 0x1ff3
> +#define M48T59_ALARM_SEC 0x1ff2
> +#define M48T59_UNUSED 0x1ff1
> +#define M48T59_FLAGS 0x1ff0
> +
> +#define M48T59_WDAY_CB 0x20 /* Century Bit */
> +#define M48T59_WDAY_CEB 0x10 /* Century Enable Bit
> */
> +
> +#define M48T59_CNTL_READ 0x40;
> +#define M48T59_CNTL_WRITE 0x80;
> +
> +#define M48T59_FLAGS_WDT 0x80 /* watchdog timer expired */
> +#define M48T59_FLAGS_AF 0x40 /* alarm */
> +#define M48T59_FLAGS_BF 0x10 /* low battery */
> +
> +#define M48T59_INTR_AFE 0x80 /* Alarm Interrupt
> Enable */
> +#define M48T59_INTR_ABE 0x20
>
Another style is to put the flag and control register values
immediately after the register, indenting the values an additional tab
to distinguish them from the list of registers. Either way is ok with
me.
> +/**
> + * NOTE: M48T59 only uses BCD mode
> + */
> +static int m48t59_rtc_read_time(struct device *dev, struct rtc_time
> *tm)
> +{
> + unsigned char val;
> +
> + /* Issue the READ command */
> + M48T59_WRITE((M48T59_READ(M48T59_CNTL) | 0x40), M48T59_CNTL);
> +
...
> + /* Clear the READ bit to restore the update */
> + M48T59_WRITE((M48T59_READ(M48T59_CNTL) & ~0x40), M48T59_CNTL);
Should you clear READ and WRITE when your driver starts in case the
previous driver got interrupted (say the system crashed)? Or is it ok
for READ and WRITE to be set?
You aren't using the READ and WRITE flag bits you defined above. If
the line gets too long, you might create a SET_BITS / CLEAR_BITS macro.
milton
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