[PATCH]: Add 8548 pcie bus number workaround

[Zang Roy-r61911]

On Thu, 2007-06-07 at 14:48, Kumar Gala wrote:
> On Jun 6, 2007, at 10:19 PM, Zang Roy-r61911 wrote:
> 
> >
> > From: Zang Roy-r61911 <tie-fei.zang at freescale.com>
> >
> > Remove legacy pcie support for 8641 chip.
> > General PCI code can fully support 8641 Rev2.0 chip.
> > For 8548 PEX controller, PCIE host controller configure
> > space can only be accessed as "bus->number = 0" in
> > the PCI architecture. So "bus->number == hose->bus_offset"
> > judgment is added.
> 
> Uugh, I'm completely confused.  Does 8548 rev 2.x have some errata  
> (or 'feature') that 8641 doesn't have?
NO! I do not think so!
It is a story about the 85xx/86xx pcie road map.
Originally, fsl_pcie.c is based on the pcie support code for 86xx (1.x
or later).

Jdl and I separate this part of code for the purpose to support both
85xx/86xx pcie. So this part of code contains some garbage code for
legacy 86xx pcie support or debug information. I have discussed this
with the original developer.

So in this patch I remove the unused code. Is it wrong?
Now this file is target to support 8548 rev 1.x and 2.x pcie controller.
Now, I am working to put some common code to support 85xx/86xx pcie in
this file, such as atmu init and link status check.

Moer patches will be posted to provide a completely pcie support for
85xx/86xx.

Thanks.
Roy