[PATCH 49/61] 8xx: Update device trees.

[Segher Boessenkool]

> -			d-cache-line-size = <20>;	// 32 bytes
> -			i-cache-line-size = <20>;	// 32 bytes
> -			d-cache-size = <2000>;		// L1, 8K
> -			i-cache-size = <4000>;		// L1, 16K
> +			d-cache-line-size = <d#32>;
> +			i-cache-line-size = <d#32>;
> +			d-cache-size = <d#8192>;
> +			i-cache-size = <d#16384>;

IMHO this isn't an improvement, but it's your tree :-)
You removed the comment that those caches are L1; is
there an L2 cache on this CPU?

> -		mpc8xx_pic: pic at ff000000 {
> +		PIC: pic at 0 {

interrupt-controller at 0

> -			cpm_pic: pic at 930 {
> +			CPM_PIC: pic at 930 {

similar

> +				compatible = "fsl,mpc866-smc-uart",
> +				             "fsl,cpm1-smc-uart",
> +				             "fsl,cpm1-uart",
> +				             "fsl,cpm-smc-uart",
> +				             "fsl,cpm-uart";

Do you need _all_ of these?  :-)

> +				fsl,cpm-brg = <1>;
> +				fsl,cpm-command = <0090>;

Are these two documented?  Your patch queue is too
long for me to check for myself.

> -	soc885 at ff000000 {
> +	bcsr at ff080000 {

Maybe use a more generic name, I have no idea what a
"BCSR" is.

Good improvements over all, thank you!


Segher