[Fastboot] [PATCH] Fix interrupt distribution in ppc970

[Mohan Kumar M]

On Mon, Dec 18, 2006 at 04:27:06PM +0530, Mohan Kumar M wrote:
> On Mon, Dec 18, 2006 at 03:37:36PM +1100, Paul Mackerras wrote:
> > 
> > It feels hacky to be basing this sort of thing on the PVR.  I would
> > like to understand the real problem better.  Is it that we are
> > sometimes setting default_distrib_server to point to a CPU which is
> > not running?  If so, why and how?
> 
> At the time of kexec/kdump shutdown sequence all secondary processors
> are removed from the Global Interrupt Queue by calling the corresponding
> rtas-set-indicator call. So even though default_distrib_server is 0xff
> PIC should distribute the interrupts only to the processors available in
> GIQ (please correct me if I am wrong), but its not happening in our
> JS20 box. Our JS20 firmware version is FW04310120 dated 07/26/04.
>
> > Is this something that is specific
> > to the firmware on IBM 970-based blade systems?  Is there in fact a
> > firmware bug that this works around?
> 
> Looks like a firmware bug, since I am not able to reproduce this problem
> on a JS21 box with the firmware version MB240_470 dated 03/23/2006. I am
> planning to upgrade JS20 with latest firmware and test with maxcpus=1
>

Even after updating the JS20 box with the latest firmware FW06470160
dated 11/21/06, we are facing the same problems with "maxcpus=1" kernel
parameter. As mentioned earlier, we do not have this problem on JS21
hardware. JS20 has PPC970 cpus while JS21 has PPC970MP cpus. Could it be
a reason? Still we are not able to conclude whether it is related to
firmware or not.

Paul, can you tell us which approach we can follow to solve this
problem? The patch I have sent earlier was hackish. So do we need to use
"noirqdistrib" kernel parameter in addition to "maxcpus=1" to avoid
these problems?

Mohan.

 
> > Why don't we see it on non-970
> > based systems?
> 
> I have seen secondary thread related interrupt distribution problems on
> POWER5 boxes and I fixed it sometime back. Since POWER4 does not have
> SMT there is no interrupt distribution problem.
> 
> > 
> > Paul.