[PATCH] powerpc: document new interrupt-array property

[Segher Boessenkool]

>> Not really a hack, this is documented in the interrupt
>> binding:
>
> No, it really is a hack, I'm afraid.  interrupt-map doesn't in general
> make sense for mapping interrupt-children which are not physical
> children.  Why?  Because the interrupt map includes unit specifiers,
> which means the expected addressing format in the interrupt map must
> match that of the reg property in every node mapped through it.

Hrm I guess I misunderstood the way you do things now.
Could you give an example?  I'm too lazy to look up
the DTS file :-)

> We get away with it in this case because we ignore the unit specifier
> part,

That's perfectly fine for many interrupt maps.

> and the kernel parser happens to use the interrupt parent's
> #address-cells value, rather than the physical parent's.

For the child interrupt specifiers, the "#address-cells"
value in the node containing the "interrupt-map" itself
should be used.  For the parent interrupt specifier, the
"#address-cells" value in whatever node the "interrupt-map"
for the matching entry points to should be used.

It sounds like the kernel does the right thing here?

[Of course the #a value better be the same as the value
in the physical parent, and all nodes mapping via a
particular "interrupt-map" better have unique unit
address for that map].

>>> 3.3.  "interrupt-map" property
>>> At any level in the interrupt tree, a mapping may need to take
>>> place between the child interrupt domain and the parent’s.  This
>>> is represented by a new property called "interrupt-map".
>>
>> Note it says "*any* level".
>
> We could do this properly via an interrupt map by placing the MAL
> under a MAL-interrupt-nexus node, which exists to do nothing but remap
> the interrupts.  That's pretty horrible, though.

It doesn't have to physically be under there, only in the
*interrupt* tree.  This situation isn't specific to your
situation; it happens in other cases with weird wiring
too.

>> As an added bonus you end up
>> with one single namespace for the interrupts (one interrupt
>> domain in interrupt-mapping speak), which is probably what
>> the chip documentation does as well.
>
> No, actually.  Afaict for the 4xx chips, the user manuals just give
> the interrupt mapping in tables in the the chapter on the interrupt
> controllers.  There's a separate table, with separate interrupt
> numbers for each UIC.

Oh okay.


Segher