[PATCH] advertise correct IDE mode on Pegasos2

[Matt Sealey]

The programming interface register is definitely writable, but the VIA IDE docs
state that certain bits will always read 0 - setting '0x5' in my original patch
set those two bits so it was forced into native mode if it wasn't already.

Setting them to ~0x5 will set them to 0 (legacy mode) and they will always read
back as 0 (legacy mode.. sigh) even if in native mode.

Fixing the class code in the device tree doesn't mean anything as lspci, sysfs
etc. read right from config space and NOTHING in linux powerpc uses the device
tree for information (RTAS is about as close as it gets).

I'm still working on my little "device tree fixups" Forth script for Pegasos
which is very difficult without a Pegasos to test it on. I need the correct
device locations and target values to do it, and I want to add a fix so that
it ONLY runs on 20040810 firmwares (and the minor updates for 2B5 boards) and
complains on anything else (any developers who got a beta firmware..) as it
seems the fixes you're making here do not apply.

I attached it if anyone wants to toy with it.. I can't guarantee that it
even parses as I've just been poking at it, but the basic theory is in there.
It should remove any kernel/prom_init device tree fixups but requires still the
pci fixups in chrp/pci.

There's an Efika one too..

Any comments would be awesome.

-- 
Matt Sealey <matt at genesi-usa.com>
Genesi, Manager, Developer Relations

Olaf Hering wrote:
> On Fri, Aug 17, Olaf Hering wrote:
> 
> Still not 100% perfect.
> 
>> +		prom_printf("Fixing up IDE class-code on Pegasos...\n");
>> +		rc = prom_getprop(ph, "class-code", prop, sizeof(u32));
>> +		if (rc == sizeof(u32)) {
>> +			prop[0] &= ~0x5;
>> +			prom_setprop(ph, name, "class-code", prop, sizeof(u32));
>> +		}
> 
> This updates the class code in the device-tree, but sysfs still shows
> the old value.
> 
>> +	pci_read_config_byte(viaide, PCI_CLASS_PROG, &progif);
>> +	pci_write_config_byte(viaide, PCI_CLASS_PROG, progif & ~0x5);
> 
> Is this a readonly register by any chance?
> Appending a 'viaide->class &= ~0x5;' changes the code paths in
> do_ide_setup_pci_device(), now IDE prints 'not 100%% native mode,
> will probe irqs later'. Where are the irqs supposed to come from?
> 
>> -#ifdef CONFIG_PPC_CHRP
>> -	if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
>> -		hwif->irq = hwif->channel ? 15 : 14;
>> -	}
>> -#endif
> 
> Maybe we should just leave this in and dont bother about the arch
> specific tweak?
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