[Cbe-oss-dev] [patch 3/3] cell: prevent alignment interrupt on local store
segher at kernel.crashing.org
Fri Apr 13 05:57:45 EST 2007
> I don't know how many versions of libc you are currently building, but
> probably makes sense to have at least one that uses altivec, and one
> in-order (e.g. cell) and out-of-order (e.g. power5) pipelines each.
Something compiled for one in-order CPU will not run
very well on any other in-order CPU; each has specific
hazards (like any CPU core, but on in-order it tends
to _hurt_ if you hit any).
(Almost) all "generic" optimisations for in-order cores
(schedule dependent insns far apart, ...) help even
*more* on OoOE cores since those tend to be wider.
The big issue on the Cell PPU is that it simply cannot
execute half of the insns in the PowerPC architecture
at a reasonable speed.
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