[PATCH]: powerpc: clarify use of twi/isync in io macros

[Segher Boessenkool]

>> + * A data-dependent branch followed by an isync ensures that no
>> + * instructions after the isync in program order will be
>> + * (speculatively) executed, so the load that the twi depends
>> + * on has to complete before anything else is executed; in
>
> While the statement about branches is true, it's not especially
> relevant when it comes to twi.

twi is a data-dependent branch -- all exceptions are branches (well
they do change the execution flow!), and this one is generated
directly by an insn even.  Traps and "normal" branches are neighbours
in the opcode maps, too, FWIW ;-)

> What's happening is that isync has to
> prevent any following instructions from starting execution until all
> previous instructions have completed, meaning that they have got to
> the point of knowing whether they will generate an exception or not.

It also has to know whether the isync will be executed at all, in
the sequential model.

> In general the processor doesn't know whether twi will generate an
> exception until the data it depends on is available, and that's why
> the isync has to wait for the previous load to have returned the
> data.

Yeah, the main point is that the load insn can complete _before_
the data has come back ("the storage access has been performed"),
so an isync without another insn depending on the load result
won't do.

Care to write some better explanatory text than the rubbish I
came up with?  :-)

Btw, you say "in general the CPU doesn't know", but it _can_ know
in this code, as the TO field is 0 (so it can never trap).  Is
there anything preventing/forbidding a CPU from optimising this
case?  I see it spelled out for "conditional branch" insns, but
it would be interesting to know if the arch guarantees no insn
will complete before its input regs are ready.