[patch 0/5] [v2] powerpc: PA Semi PWRficient patches

[Olof Johansson]

Hi,

The following series of patches introduces basic support for PA Semi's
PA6T core, and the base platform support for PWRficient PA6T-1682M.

It is split up in 5 separate patches:

1. Reduce default cacheline size to 64 bytes
2. Divorce CPU_FTR_CTRL from CPU_FTR_PPCAS_ARCH_V2_BASE
3. Cpu table entry, PVR value
4. Basic arch/powerpc/platforms/pasemi contents
5. MAINTAINER entry


Changes since last submission:

* Include file cleanup (Roland)
* Whitespace/line length fixes (Mikey, Joel)
* Kill linux,pci-domain stuff (Ben)
* Remove loops_per_jiffy default (Ben)
* Enforce PCI-e config space addressing (Ben)
* Whitespace, init, cast fixes (Arnd)
* Prototypes -> pasemi.h (Arnd)
* Kill some of the RTC stubs (Arnd)


-Olof