Recently removed io accessors

Peter Korsgaard jacmet at
Fri Oct 13 16:56:34 EST 2006

>>>>> "BH" == Benjamin Herrenschmidt <benh at> writes:


>> Any chance of getting them back or should I implement a (slower)
>> loop myself before submitting the patch?

BH> Well, a "packet buffer" should have no endian. When streaming in
BH> our out a fifo, you basically stream bytes that happen to come out
BH> 2 at a time.  So unless somebody wired the hardware backward, you
BH> should do no swapping when using the fifo.

I agree in principle, but the issue gets complicated by the fact that
the chip works in chunks of 32bit, but the 911{5..7} chips only have a
16bit interface to lower costs, and that the chip has a builtin endian
swap feature (which works for all direct registers, but apparently not
for the packet buffers).

The memory controller automatically translates a 32bit access to two
16 bit accesses.

You could be right that the hw people screwed something up, but that
doesn't help much once there's units in the field :/

Bye, Peter Korsgaard

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