[PATCH 1/2]: powerpc/cell spidernet bottom half
rick.jones2 at hp.com
Thu Aug 17 09:08:34 EST 2006
Linas Vepstas wrote:
> On Wed, Aug 16, 2006 at 11:24:46PM +0200, Arnd Bergmann wrote:
>>seems to be hard to make it go fast using any of them.
> Last round of measurements seemed linear for packet sizes between
> 60 and 600 bytes, suggesting that the hardware can handle a
> maximum of 120K descriptors/second, independent of packet size.
> I don't know why this is.
DMA overhead perhaps? If it takes so many micro/nanoseconds to get a
DMA going.... That used to be a reason the Tigon2 had such low PPS
rates and issues with multiple buffer packets and a 1500 byte MTU - it
had rather high DMA setup latency, and then if you put it into a system
with highish DMA read/write latency... well that didn't make it any
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