PowerPC paxtest results w/ gcc-4.1

Gabriel Paubert paubert at iram.es
Wed Aug 16 20:59:25 EST 2006

On Tue, Aug 15, 2006 at 01:59:05PM +1000, Paul Mackerras wrote:
> Matt Sealey writes:
> > Book I compatible PowerPC's have had a "no-executable" bit in
> > the page protection flags since the dark ages.. see page 7-38
> > and 7-39 of the 'Programming Environments Manual for 32-Bit
> > Microprocessors'.. this document predates even the G3.
> What are you referring to?  I have a copy of the PEM from pre-G3 days,
> and a copy that I downloaded just now, and neither of them have an N
> bit in the PTE (and yes I just looked carefully through pages 7-38 and
> 7-39).
> There is an N bit in the segment register format, and that's what
> Albert is using.
> > As far as the documentation goes, you can make the page
> > readable and writable to the LSU, but the N bit causes the
> > instruction fetch to cause a machine check. That's pretty
> > "not-executable" to me at least :)
> A machine check is nasty, because it may not be recoverable...

I agree, but I don't know why you believe it would cause 
a machine check (0x200): from my docs, it is an ISI (0x400). 

BTW, there is one way to make pages non executable: mark
them as guarded, but it will have a significant cost in
terms of performance. 

I never understood why PTE entries waste 4 bits (WIMG)
for effectively very few valid combinations.


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