Not coherent cache DMA for G3/G4 CPUs: clarification needed

[Benjamin Herrenschmidt]

> There are many mv64x60 based platforms working just fine today with
> CONFIG_NOT_COHERENT_CACHE defined.  The reason for turning coherency off
> is that there is a bug in the bridge requiring a hardware workaround.
> Unfortunately, not all of the hardware vendors have implemented that
> workaround and I know of one that considers it infeasible and will
> not implement it.

Define "working fine" ... With the current implementation, and according
to the spec, it will randomly crap out or checkstop due to the same page
beging accessed via the NCU and being in the L2 unless you disabled
speculative loads and made sure it can't prefetch accross page
boundaries maybe ? Or set the G bit all over the BAT mapping (ouch !).

> I expect that the pegasos has that hardware workaround implemented so
> the kernel maintainers for that platform have the good fortune of being
> able to run with coherency on.

I suppose so...

> What Ben says is correct, there is that issue.  However, AFAIK, I have
> not yet to run into it.

Hrm... well, I wouldn't rely on that tho.

> If that hardware workaround is not implemented, the options are:
> a) 100% chance of a system hang with coherency on
> or
> b) < 0.0..1% chance of a system hang with coherency off (at least in my
> experience to far).
> 
> The choice is simple.

I disagree. A solution that is known to have a hole in it is no good
even if you haven't managed to trigger it so far. Now it's Gerhard's
choice.

Ben.